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april 1990 order number: 271214-002 M80C186EB-16, -13, -8 16-bit high-integration embedded processor # full static operation # true cmos inputs and outputs # b 55 cto a 125 c operating temperature range y integrated feature set e low-power static cpu core e two independent uarts each with an integral baud rate generator e two 8-bit multiplexed i/o ports e programmable interrupt controller e three programmable 16-bit timer/counters e clock generator e ten programmable chip selects with integral wait-state generator e memory refresh control unit e system level testing support (once mode) y direct addressing capability to 1 mbyte memory and 64 kbyte i/o y speed versions available: e 16 mhz (M80C186EB-16) e 13 mhz (m80c186eb-13) e 8 mhz (m80c186eb-8) y low-power operating modes: e idle mode freezes cpu clocks but keeps peripherals active e powerdown mode freezes all internal clocks y complete system development support e asm86 assembler, pl/m 86, pascal 86, fortran 86, c-86, and system utilities e in-circuit emulator (ice tm -186eb) y supports m80c187 numeric coprocessor interface y available in: e 88-lead pin grid array (mg80c186eb) the m80c186eb is a second generation chmos high-integration microprocessor. it has features that are new to the m80c186 family and include a static cpu core, an enhanced chip select decode unit, two independent serial channels, i/o ports, and the capability of idle or powerdown low power modes. 271214 1
M80C186EB-16, -13, -8 16-bit high-integration embedded processor contents page introduction 4 overview 4 m80c186eb core architecture 4 register set 4 instruction set 5 memory organization 5 addressing modes 5 data types 7 interrupts 7 bus interface unit 9 clock generator 9 m80c186eb peripheral architecture 10 interrupt control unit 10 timer/counter unit 10 serial communications unit 12 chip-select unit 12 i/o port unit 13 refresh control unit 13 power management unit 13 m80c187 interface 13 once test mode 13 package information 14 pin descriptions 14 m80c186eb pinout 19 electrical specifications 21 absolute maximum ratings 21 operating conditions 21 recommended connections 21 dc specifications 22 i cc versus frequency and voltage 23 pdtmr pin delay calculation 23 contents page ac specifications 24 ac characteristicseM80C186EB-16 24 ac characteristicsem80c186eb-13 25 ac characteristicsem80c186eb-8 26 relative timings (M80C186EB-16, -13, -8) 27 serial port mode 0 timings (M80C186EB-16, -13, -8) 28 ac test conditions 29 ac timing waveforms 29 derating curves 32 reset 33 cold reset waveforms 34 warm reset waveforms 35 bus cycle waveforms 36 register bit summary 44 m80c186eb execution timings 48 instruction set summary 49 footnotes 54 88-lead ceramic pin grid array package 55 errata 56 revision history 56 2
m80c186eb 271214 2 figure 1. m80c186eb block diagram 3
m80c186eb introduction the m80c186eb is the first product in a new gener- ation of low-power, high-integration microproces- sors. it enhances the existing 186 family by offering new features and new operating modes. the m80c186eb is object code compatible with the m80c186/m80c188 microprocessors. the feature set of the m80c186eb meets the needs of low power, space critical applications. low-power applications benefit from the static design of the cpu core and the integrated peripherals. minimum current consumption is achieved by providing a pow- erdown mode that halts operation of the device, and freezes the clock circuits. peripheral design en- hancements ensure that non-initialized peripherals consume little current. space critical applications benefit from the inte- gration of commonly used system peripherals. two serial channels are provided for services such as diagnostics, inter-processor communication, modem interface, terminal display interface, and many oth- ers. a flexible chip select unit simplifies memory and peripheral interfacing. the interrupt unit provides sources for up to 129 external interrupts and will pri- oritize these interrupts with those generated from the on-chip peripherals. three general purpose tim- er/counters and sixteen multiplexed i/o port pins round out the feature set of the m80c186eb. overview figure 1 shows a block diagram of the m80c186eb. the execution unit (eu) is an enhanced m8086 cpu core that includes: dedicated hardware to speed up effective address calculations, enhance execution speed for multiple-bit shift and rotate in- structions and for multiply and divide instructions, string move instructions that operate at full bus bandwidth, ten new instruction, and full static opera- tion. the bus interface unit (biu) is the same as that found on the original 186 family products, except the queue-status mode has been deleted and buffer in- terface control has been changed to ease system design timings. an independent internal bus is used to allow communication between the biu and inter- nal peripherals. m80c186eb core architecture register set the m8086, m8088, m80186, m80c186 and m80c188 all contain the same basic set of registers, instructions, and addressing modes. the m80c186eb is upward compatible with all of these microprocessors. the m80c186eb base architecture has fourteen 16-bit registers as shown in figure 2. there are eight general purpose registers which may be used for arithmetic and logic operands. four of these regis- ters (ax, bx, cx and dx) can be used as 16-bit registers or split into pairs of separate 8-bit registers. the other four registers (bp, si, di and sp) may also be used to determine offset addresses of operands in memory. these registers may contain base ad- dresses or indexes to particular locations within a segment. the addressing mode selects the specific registers for operand and address calculations. another four 16-bit registers (cs, ds, es, ss) select the segments of memory that are immediately ad- dressable for code, stack, and data. there are two remaining special purpose registers (ip and f) that record or alter certain aspects of the m80c186eb processor state. 15 0 ah al ax bh bl bx ch cl cx dh dl dx source index si destination index di base pointer bp stack pointer sp code segment cs stack segment ss data segment ds extra segment es instruction pointer ip flags f figure 2. m80c186eb register set 4
m80c186eb instruction set the instruction set is divided into seven categories: data transfer, arithmetic, shift/rotate/logical, string manipulation, control transfer, high-level instruc- tions, and processor control. these categories are summarized in figure 4. an m80c186eb instruction can reference anywhere from zero to several operands. an operand can reside in a register, in the instruction itself, or in memory. memory organization memory is organized in sets of segments. each seg- ment is a linear contiguous sequence of up to 64k (2 16 ) 8-bit bytes. memory is addressed using a two- component address (a pointer) that consists of a 16-bit base segment and a 16-bit offset. the 16-bit base segment values are contained in one of four internal segment registers (code, data stack, extra). the physical address is calculated by shifting the base value left by four bits and adding the 16-bit offset value to yield a 20-bit physical address (see figure 3). the resulting 20-bit address allows for a 1 mbyte address range. 271214 3 figure 3. two component address all instructions that address operands in memory must specify the base segment and the 16-bit offset value. for speed and compact instruction encoding, the segment register used for a physical address generation is implied by the addressing mode used (see table 1). special segment override instruction prefixes allow the implicit segment register selection rules to be overridden for special cases. the code, stack, data, and extra segments may coincide for simple programs. table 1. segment register selection rules memory segment implicit segment reference register selection rule needed used instructions code (cs) instruction prefetch and immediate data stack stack (ss) all stack pushes and pops; any memory references which use the bp register as a base external extra (es) all string instruction references which use the di register as an index local data data (ds) all other data references addressing modes the m80c186eb provides eight categories of ad- dressing modes to specify operands. two address- ing modes are provided for instructions that operate on register or immediate operands: # register operand mode: the operand is located in one of the 8- or 16-bit general registers. # immediate operand mode: the operand is in- cluded in the instruction. six modes are provided to specify the location of an operand in a memory segment. a memory operand address consists of two 16-bit components: a seg- ment base and an offset. the segment base is sup- plied by a 16-bit segment register either implicitly chosen by the addressing mode or explicitly chosen by a segment override prefix. the offset, also called the effective address, is calculated by summing any combination of the following three address ele- ments: # the displacement (an 8- or 16-bit immediate value contained in the instruction); # the base (contents of either the bx or bp base registers); and # the index (contents of either the si or di index registers). 5
m80c186eb general purpose mov push pop pusha popa xchg xlat input/output in out address object lea lds les flag transfer lahf sahf pushf popf addition add inc aaa daa substraction sub sbb dec neg cmp aas das multiplication mul imul aam division div idiv aad cbw cwd string operations movs ins outs cmps scas lods stos rep repe/repz repne/repnz logicals not and or xor test shifts shl/sal shr sar rotates rol ror rcl rcr flag operations stc clc cmc std cld sti cli external synchronization hlt wait lock no operation nop high level instructions enter leave bound conditional transfers ja/jnbe jae/jnb jb/jnae jbe/jna jc je/jz jg/jnle jge/jnl jl/jnge jle/jng jnc jne/jnz jno jnp/jp0 jns jo jp/jpe js unconditional transfers call ret jmp iteration controls loop loope/loopz loopne/loopnz jcxz interrupts int into iret figure 4. m80c186eb instruction set 6
m80c186eb any carry out from the 16-bit addition is ignored. 8-bit displacements are sign extended to 16-bit val- ues. combinations of these three address elements de- fine the six memory addressing modes, described below. # direct mode: the operand's offset is contained in the instruction as an 8- or 16-bit displacement el- ement. # register indirect mode: the operand's offset is in one of the registers si, di, bx, or bp. # based mode: the operand's offset is the sum of an 8- or 16-bit displacement and the contents of a base register (bx or bp). # indexed mode: the operand's offset is the sum of an 8- or 16-bit displacement and the contents of an index register (si or di). # based indexed mode: the operand's offset is the sum of the contents of a base register and an index register. # based indexed mode with displacement: the op- erand's offset is the sum of a base register's con- tents, an index register's contents, and an 8- or 16-bit displacement. data types the m80c186eb directly supports the following data types: # integer: a signed binary numeric value contained in an 8-bit byte or 16-bit word. all operations as- sume a 2's complement representation. signed 32- and 64-bit integers are supported using the m80c187 numerics coprocessor. # ordinal: an unsigned binary numeric value con- tained in an 8-bit byte or 16-bit word. # pointer: a 16- or 32-bit quantity, composed of a 16-bit offset component, or a 16-bit segment base component and a 16-bit offset component. # string: a contiguous sequence of bytes or words. a string may contain from 1 kbyte to 64 kbytes. # ascii: a byte representation of alphanumeric and control characters using the ascii standard of character representation. # bcd: a byte (unpacked) representation of the decimal digits 0 9. # packed bcd: a byte (packed) representation of two decimal digits (0 9). one digit is stored in each nibble (4 bits) of the byte. # floating point: a signed 32-, 64- or 80-bit real number representation. floating point operands are supported when using the m80c187 numeric coprocessor. in general, individual data elements must fit within defined segment limits. interrupts an interrupt transfers execution to a new program location. the old program address (cs:ip) and ma- chine state (f) are saved on the stack to allow re- sumption of the interrupted program. interrupts fall into three classes: hardware initiated, software (pro- gram) initiated, and instruction exception initiated. hardware initiated interrupts occur in response to an external or internal input and are classified as non- maskable or maskable. programs may cause an interrupt by executing the ``int'' instruction. instruction exceptions occur when an illegal opcode has been fetched into the queue and is read by the execution unit. another type of exception can be generated when executing an ``esc'' instruction. for all cases except the ``esc'' exception, the return address from an exception will point at the instruc- tion immediately following the instruction causing the exception. the return address after an ``esc'' exception will point back to the esc instruction causing the exception, or to the segment override prefix immediately preceding the esc instruction if the prefix was present. a table containing up to 256 pointers defines the proper interrupt service routine for each interrupt. in- terrupts 0 31 are reserved by intel. table 2 shows the m80c186eb predefined type and default priority levels. for each interrupt, an 8-bit vector (vector type) identifies the appropriate table entry. multiply- ing the 8-bit vector by 4 defines the vector address. int instructions contain or imply the vector type and allow access to all 256 interrupts. 7
m80c186eb table 2. m80c186eb interrupt vectors interrupt vector vector default related name type address priority instructions divide error 0 00h 1 div, idiv single step interrupt 1 04h 1a all non-maskable interrupt 2 08h 1 int 2 or nmi one byte interrupt 3 0ch 1 int interrupt on overflow 4 10h 1 int0 array bounds check 5 14h 1 bound invalid op-code 6 18h 1 illegal inst esc op-code interrupt 7 1ch 1 esc op-codes timer 0 interrupt 8 20h 2 reserved 9 11 24h 2ch int0 interrupt 12 30h 5 int1 interrupt 13 34h 6 int2 interrupt 14 38h 7 int3 interrupt 15 3ch 8 numerics exception 16 40h 1 esc op-codes int4 interrupt 17 44h 4 timer1 interrupt 18 48h 2a timer2 interrupt 19 4ch 2b uart 0 receive interrupt 20 50h 3 uart 0 transmit interrupt 21 54h 3a reserved 22 31 58h 7ch 8
m80c186eb bus interface unit the m80c186eb core incorporates a bus controller that generates local bus control signals. in addition, it employs a hold/hlda protocol to share the local bus with other bus masters. the bus controller is responsible for generating 20 bits of address, read and write strobes, bus cycle status information, and data (for write operations) in- formation. it is also responsible for reading data off the local bus during a read operation. a ready in- put pin is provided to extend a bus cycle beyond the minimum four states (clocks). a hold/hlda protocol is provided by the local bus controller to allow multiple bus masters to share the same local bus. when the m80c186eb relinquishes control of the local bus, it floats certain bus control signals to allow another bus master to drive these pins directly. refer to the pin description section to determine which pins the m80c186eb will float dur- ing a hold/hlda bus exchange. the m80c186eb local bus controller also generates two control signals (den and dt/r ) when interfac- ing to external transceiver chips. this capability al- lows the addition of transceivers for simple buffering of the mulitplexed address/data bus. clock generator the m80c186eb provides an on-chip clock genera- tor for both internal and external clock generation. the clock generator features a crystal oscillator, a divide-by-two counter, and two low-power operating modes. the oscillator circuit is designed to be used with ei- ther a parallel resonant fundamental or third-over- tone mode crystal network. alternatively, the oscilla- tor circuit may be driven from an external clock source. figure 5 shows the various operating modes of the m80c186eb oscillator circuit. the crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter. this counter is used to drive all internal phase clocks and the exter- nal clkout signal. clkout is a 50% duty cycle processor clock and can be used to drive other sys- tem components. all ac timings are referenced to clkout. the following parameters are recommended when choosing a crystal: temperature range: application specific esr (equivalent series resistance): 40 x max c0 (shunt capacitance of crystal): 7.0 pf max c l (load capacitance): 20 pf g 2pf drive level: 1 mw max 271214 4 (a) crystal connection note: the l 1 c 1 network is only required when using a third- overtone crystal. 271214 5 (b) clock connection figure 5. m80c186eb clock configurations 9
m80c186eb m80c186eb peripheral architecture the m80c186eb has integrated several common system peripherals with a cpu core to create a com- pact, yet powerful system. the integrated peripher- als are designed to be flexible and provide logical interconnections between supporting units (e.g., the interrupt control unit supports interrupt requests from the timer/counters or serial channels). the list of integrated peripherals include: # 7-input interrupt control unit # 3-channel timer/counter unit # 2-channel serial communications unit # 10-output chip-select unit # i/o port unit # refresh control unit # power management unit the registers associated with each integrated peri- heral are contained within a 128 x 16 register file called the peripheral control block (pcb). the pcb can be located in either memory or i/o space on any 256 byte address boundary. during bus cycles that access the pcb, the bus controller will signal the operation externally (i.e., the rd ,wr , status, address, data, etc., lines will be driven as in a normal bus cycle). however, ready is ignored and the con- tents of the data bus during a read operation is ig- nored. the starting address of the pcb is controlled by a relocation register and can overlap any of the mem- ory or i/o regions programmed into the chip select unit. in this case, the overlapped chip select will not go active when the pcb is read or written. figure 6 provides a list of the registers associated with the pcb. the register bit summary at the end of this specification individually lists all of the regis- ters and identifies each of their programming attri- butes. interrupt control unit the m80c186eb can receive interrupts from a num- ber of sources, both internal and external. the inter- rupt control unit serves to merge these requests on a priority basis, for individual service by the cpu. each interrupt source can be independently masked by the interrupt control unit (icu) or all interrupts can be globally masked by the cpu. internal interrupt sources include the timers and se- rial channel 0. external interrupt sources come from the five input pins int4:0. the nmi interrupt pin is not controlled by the icu and is passed directly to the cpu. although the timer and serial channel each have only one request input to the icu, sepa- rate vector types are generated to service individual interrupts within the timer and serial channel units. the m80c186eb icu provides a mechanism for ex- panding the number of external interrupt sources. two pairs of pins can be independently configured to support an external slave interrupt controller (82c59a). each pair of external pins can be expand- ed to support 64 interrupts, making it possible for the m80c186eb to support a total of 129 external inter- rupts. the icu may be used in a polled mode if interrupts are undesirable. when polling, the processor dis- ables interrupts and then polls the icu whenever it is convenient. timer/counter unit the m80c186eb timer/counter unit (tcu) pro- vides three 16-bit programmable timers. two of these are highly flexible and are connected to exter- nal pins for control or clocking. a third timer is not connected to any external pins and can only be clocked internally. however, it can be used to clock the other two timer channels. the tcu can be used to count external events, time external events, gen- erate non-repetitive waveforms, generate timed in- terrupts, etc. each timer has at least one 16-bit compare register and one 16-bit count register. timers 0 and 1 each have an additional 16-bit compare register. the count register is incremented every fourth cpu clock cycle (internal clocking), every time timer2 expires (timers 0 and 1 only), or every low-to-high tran- sition on the timer input pin (timers 0 and 1 only). the input clock to timers 0 and 1 must not exceed one fourth the operating frequency of the m80c186eb. when the count register matches the value programmed into the compare register, sever- al operations may happen. all three timers can generate an interrupt when the compare register matches the value in the count register. additionally, timers 0 and 1 have an output pin that can change state or pulse when the com- pare condition occurs. 10
m80c186eb pcb function offset 00h reserved 02h end of interrupt 04h poll 06h poll status 08h interrupt mask 0ah priority mask 0ch in-service 0eh interrupt request 10h interrupt status 12h timer control 14h serial control 16h int4 control 18h int0 control 1ah int1 control 1ch int2 control 1eh int3 control 20h reserved 22h reserved 24h reserved 26h reserved 28h reserved 2ah reserved 2ch reserved 2eh reserved 30h timer0 count 32h timer0 compare a 34h timer0 compare b 36h timer0 control 38h timer1 count 3ah timer1 compare a 3ch timer1 compare b 3eh timer1 control pcb function offset 40h timer2 count 42h timer2 compare 44h reserved 46h timer2 control 48h reserved 4ah reserved 4ch reserved 4eh reserved 50h reserved 52h port0 pin 54h port0 control 56h port0 latch 58h port1 direction 5ah port1 pin 5ch port1 control 5eh port1 latch 60h serial0 baud 62h serial0 count 64h serial0 control 66h serial0 status 68h serial0 rbuf 6ah serial0 tbuf 6ch reserved 6eh reserved 70h serial1 baud 72h serial1 count 74h serial1 control 76h serial1 status 78h serial1 rbuf 7ah serial1 tbuf 7ch reserved 7eh reserved pcb function offset 80h gcs0 start 82h gcs0 stop 84h gcs1 start 86h gcs1 stop 88h gcs2 start 8ah gcs2 stop 8ch gcs3 start 8eh gcs3 stop 90h gcs4 start 92h gcs4 stop 94h gcs5 start 96h gcs5 stop 98h gcs6 start 9ah gcs6 stop 9ch gcs7 start 9eh gcs7 stop a0h lcs start a2h lcs stop a4h ucs start a6h ucs stop a8h relocation aah reserved ach reserved aeh reserved b0h refresh base b2h refresh time b4h refresh control b6h refresh address b8h power control bah reserved bch step id beh reserved pcb function offset c0h reserved c2h reserved c4h reserved c6h reserved c8h reserved cah reserved cch reserved ceh reserved d0h reserved d2h reserved d4h reserved d6h reserved d8h reserved dah reserved dch reserved deh reserved e0h reserved e2h reserved e4h reserved e6h reserved e8h reserved eah reserved ech reserved eeh reserved f0h reserved f2h reserved f4h reserved f6h reserved f8h reserved fah reserved fch reserved feh reserved figure 6. m80c186eb peripheral control block registers 11
m80c186eb other timer programming options include: # all three timers can be set to halt or continue after a compare match. # timers 0 and 1 can be reset or retriggered using their respective input pins. # tcu registers can be read or written at any time. serial communications unit the serial control unit (scu) of the m80c186eb contains two independent channels. each channel is identical in operation except that only channel 0 is supported by the integrated interrupt controller (channel 1 has an external interrupt pin). each channel has its own baud rate generator that is in- dependent of the timer/counter unit, and can be internally or externally clocked at up to one half the m80c186eb operating frequency. each serial channel supports one synchronous and four asynchronous modes of operation and is com- patible with the serial ports of the mcs -51 and mcs -96 family of products. data field length can be 7-, 8-, or 9-bits with optional odd or even parity (generated and checked) and one stop bit (generat- ed and checked). the 9-bit mode has an optional ``addressing'' feature to simplify interprocessor com- munication. each serial port is doubled buffered in both transmit and receive operation (data can be read or written to a buffer register while data is shift- ed into or out of a shifting register, respectively). a clear-to-send input pin can be programmed to prevent data transmission if the pin is sampled inac- tive. serial channel 0 is supported by the integrated interrupt controller, providing separate receive and transmit vector types. serial channel 1 has an exter- nal interrupt pin which or's the receive and transmit interrupts. this external interrupt pin can be routed to either the external pins of the icu, the nmi pin, or any other external system interrupt controller. status bits are provided to allow polling of the serial chan- nels if interrupts are not desired. independent baud rate generators are provided for each of the serial channels. for the asynchronous modes, the generator supplies an 8x baud clock to both the receive and transmit register logic. a 1x baud clock is provided in the synchronous mode. additional features of the scu include: # framing error, receive buffer overrun error, and parity error detection. # break detect. # break send. chip-select unit the m80c186eb chip-select unit (csu) integrates logic which provides up to ten programmable chip- selects to access both memories and peripherals. in addition, each chip-select can be programmed to automatically insert additional clocks (wait-states) into the current bus cycle and automatically termi- nate a bus cycle independent of the condition of the ready input pin. each of the chip-selects can be programmed to go active for either memory or i/o accesses. ucs is the only chip-select that is active after a reset and is enabled for memory addresses in the range 0ffc00h to 0fffffh (this allows a boot-rom to be accessed using ucs ). every chip-select has a programmable start and stop register that defines the active region for the chip-select, and the ready characteristics for the region. the start and stop address fields are 10 bits in length and are matched against the upper 10 bits of either the memory or i/o address. a 10-bit compare results in a granularity of 1 kbytes for memory ac- cesses and 64 bytes for i/o accesses. each chip select can be disabled by programming its start ad- dress greater than its stop address or by clearing its enable bit. each chip-select can be programmed to automati- cally insert wait-states, and to control whether the external ready input is to be ignored or used. the m80c186eb bus controller will wait the programmed number of wait-states before the external ready pin can be used to extend or terminate the bus cy- cle. overlapping of chip-selects is allowed. however, each one that overlaps will go active. if any overlap- ping chip-select has been programmed to use exter- nal ready, the bus control unit will insert the least amount of programmed wait-states programmed be- fore the external ready pin is used. if all overlapped chip-selects ignore external ready, the bus controller will insert the maximum number of programmed wait-states. any chip-select that overlaps the periph- eral control block (pcb) will not go active for that portion of the address range allocated to the pcb. 12
m80c186eb the generic chip-selects (gcs7:0) are multiplexed with an output only port function. any channel that is being used as a chip-select must be disabled as a port pin by correctly programming the port pin con- trol registers (see the following section). i/o port unit the i/o port unit (ipu) on the m80c186eb supports two 8-bit channels of input, output, or input/output operation. port 1 is multiplexed with the chip select pins and is output only. most of port 2 is multiplexed with the serial channel pins. port 2 pins are limited to either an output or input function depending on the operation of the serial pin it is multiplexed with. two bits of port 2 are not multiplexed with any other peripheral functions and can be used as either an input or an output function. a port direction register is used to define the function of the port pin. the output for these two pins are open drain. besides a direction register, each port channel has a data latch register, port pin register, and a port multi- plexer control register. refresh control unit the refresh control unit (rcu) automatically gen- erates a periodic memory read bus cycle to keep dynamic or pseudo-static memory refreshed. a 9-bit counter controls the number of clocks between re- fresh requests. a 12-bit address generator is maintained by the rcu and is presented on the a12:1 address lines during the refresh bus cycle. the address generator is in- cremented only after the refresh bus cycle is run. this ensures that all address combinations will be presented to the memory array even if the refresh bus cycle is not run before another request is gener- ated. address bits a19:13 are programmable to al- low the refresh address block to be located on any 8 kbyte boundary. the chip-select unit is active during refresh bus cy- cles. this means that a chip-select will go active if the refresh address is within the limits specified for the channel. in addition, bhe and a0 are both driven high during refresh bus cycles (this is normally an invalid bus condition). data on the ad15:0 bus is ignored. a pending refresh request will attempt to abort a hold/hlda bus exchange. hlda is deasserted when a refresh request is pending and a bus hold is already in progress. hold must then be released in order for the m80c186eb to execute the refresh bus cycle. power management unit the m80c186eb power management unit (pmu) is provided to control the power consumption of the device. the pmu provides three power modes: ac- tive, idle, and powerdown. active mode indicates that all units on the m80c186eb are functional and the device con- sumes maximum power (depending on the level of peripheral operation). idle mode freezes the clocks of the execution and bus units at a logic zero state (all peripherals continue to operate normally). an un- masked interrupt, nmi, or reset will cause the m80c186eb to exit the idle mode. the powerdown mode freezes all internal clocks at a logic zero level and disables the crystal oscillator. all internal registers hold their values provided v cc is maintained. current consumption is reduced to just transistor junction leakage. an nmi or processor reset will cause the m80c186eb to exit the power- down mode. a timing pin is provided to establish the length of time between exiting powerdown and re- suming device operation. (length of time depends on startup time of crystal oscillator and is application dependent.) m80c187 interface the m80c186eb supports the direct connection of the m80c187 numerics coprocessor. once test mode to facilitate testing and inspection of devices when fixed into a target system, the m80c186eb has a test mode available which forces all output and in- put/output pins to be placed in the high-impedance state. once stands for ``on circuit emulation''. the once mode is selected by forcing the a19/once pin low (0) during a processor reset (this pin is weakly held to a high (1) level) while resin is ac- tive. 13
m80c186eb package information this section describes the pins, pinouts, and thermal characteristics for the m80c186eb pga package. for complete package specifications and informa- tion, see the intel packaging outlines and dimen- sions guide (order number: 231369). pin descriptions the m80c186eb pins are described in this section. table 3 presents the legend for interpreting the pin descriptions in table 4. figure 7 provides an exam- ple pin description entry. the ``i/o'' signifies that the pins are bidirectional (i.e., have both an input and output function). the ``s'' indicates that, as an input, the signal is synchronized to clkout for proper op- eration. the ``h(z)'' indicates that these pins will float while the processor is in the hold acknowledge state. r(z) indicates that these pins will float while resin is low. p(x) indicates that these pins will re- tain its current value when idle or powerdown modes are entered. all pins float while the processor is in the once mode, except oscout (oscout is required for crystal operation). name type description ad15:0 i/o these pins provide a multiplexed s(l) address and data bus. during h(z) the address phase of the bus r(z) cycle, address bits 0 through 15 p(x) are presented on the bus and can be latched using ale. 8- or 16-bit data information are transferred during the data phase of the bus cycle. figure 7. example pin description entry table 3. pin description nomenclature symbol description i input only pin o output only pin i/o pin can be either input or output e pin ``must be'' connected as described s(..) synchronous. input must meet setup and hold times for proper operation of the processor. the pin is: s(e) edge sensitive s(l) level sensitive a(..) asynchronous. input must meet setup and hold only to guarantee recognition. the pin is: a(e) edge sensitive a(l) level sensitive h(..) while the processor's bus is in the hold acknowledge state, the pin: h(1) is driven to v cc h(0) is driven to v ss h(z) floats h(q) remains active h(x) retains current state r(..) while the processor's res line is low, the pin: r(1) is driven to v cc r(0) is driven to v ss r(z) floats r(wh) weak pullup r(wl) weak pulldown p(..) while idle or powerdown modes are active, the pin: p(1) is driven to v cc p(0) is driven to v ss p(z) floats p(q) remains active (1) p(x) retains current state note: 1. any pin that specifies p(q) are valid for idle mode. all pins are p(x) for powerdown mode. 14
m80c186eb table 4. m80c186eb pin descriptions name type description v cc power connections consist of four pins which must be shorted externally to a v cc board plane. v ss ground connections consist of six pins which must be shorted externally to a v ss board plane. clkin i clock input is an input for an external clock. an external oscillator operating at two times the required m80c186eb operating frequency a(e) can be connected to clkin. for crystal operation, clkin (along with oscout) are the crystal connections to an internal pierce oscillator. oscout o oscillator output is only used when using a crystal to generate the external clock. oscout (along with clkin) are the crystal h(q) connections to an internal pierce oscillator. this pin is not to be used r(q) as 2x clock output for non-crystal applications (i.e., this pin is n.c. for p(q) non-crystal applications). oscout does not float in once mode. clkout o clock output provides a timing reference for inputs and outputs of the processor, and is one-half the input clock (clkin) frequency. h(q) clkout has a 50% duty cycle and transistions every falling edge of r(q) clkin. p(q) resin i reset in causes the m80c186eb to immediately terminate any bus cycle in progress and assume an initialized state. all pins will be a(l) driven to a known state, and resout will also be driven active. the rising edge (low-to-high) transition synchronizes clkout with clkin before the m80c186eb begins fetching opcodes at memory location 0ffff0h. resout o reset output that indicates the m80c186eb is currently in the reset state. resout will remain active as long as resin remains h(0) active. r(1) p(0) pdtmr i/o power-down timer pin (normally connected to an external capacitor) that determines the amount of time the m80c186eb waits a(l) after an exit from power down before resuming normal operation. the h(wh) duration of time required will depend on the startup characteristics of r(z) the crystal oscillator. p(1) nmi i non-maskable interrupt input causes a type-2 interrupt to be serviced by the cpu. nmi is latched internally. a(e) test /busy i test is used during the execution of the wait instruction to suspend cpu operation until the pin is sampled active (low). test a(e) is alternately known as busy when interfacing with an m80c187 numerics coprocessor. ad15:0 i/o these pins provide a multiplexed address and data bus. during the address phase of the bus cycle, address bits 0 through 15 are s(l) presented on the bus and can be latched using ale. 8- or 16-bit data h(z) information is transferred during the data phase of the bus cycle. r(z) p(x) a18:16 these pins provide multiplexed address during the address phase of the bus cycle. address bits 16 through 19 are presented on these a19/once h(z) pins and can be latched using ale. these pins are driven to a logic 0 r(wh) during the data phase of the bus cycle. during a processor reset p(x) (resin active), a19/once is used to enable once mode. a18:16 must not be driven low during reset or improper m80c186eb operation may result. 15
m80c186eb table 4. m80c186eb pin descriptions (continued) name type description s2:0 o bus cycle status are encoded on these pins to provide bus transaction information. s2:0 are encoded as follows: h(z) r(z) s2 s1 s0 bus cycle initiated p(1) 0 0 0 interrupt acknowledge 0 0 1 read i/o 0 1 0 write i/o 0 1 1 processor halt 1 0 0 queue instruction fetch 1 0 1 read memory 1 1 0 write memory 1 1 1 passive (no bus activity) ale o address latch enable output is used to strobe address information into a transparent type latch during the address phase of the bus cycle. h(0) r(0) p(0) bhe o byte high enable output to indicate that the bus cycle in progress is transferring data over the upper half of the data bus. bhe and a0 have the h(z) following logical encoding: r(z) a0 bhe encoding p(x) 0 0 word transfer 0 1 even byte transfer 1 0 odd byte transfer 1 1 refresh operation rd o read output signals that the accessed memory or i/o device must drive data information onto the data bus. h(z) r(z) p(1) wr o write output signals that data available on the data bus are to be written into the accessed memory or i/o device. h(z) r(z) p(1) ready i ready input to signal the completion of a bus cycle. ready must be active to terminate any m80c186eb bus cycle, unless it is ignored by a(l) correctly programming the chip-select unit. s(l) den o data enable output to control the enable of bi-directional transceivers when buffering a m80c186eb system. den is active only when data is to be h(z) transferred on the bus. r(z) p(1) dt/r o data transmit/receive output controls the direction of a bi-directional buffer when buffering an m80c186eb system. h(z) r(z) p(x) lock i/o lock output indicates that the bus cycle in progress is not to be interrupted. the m80c186eb will not service other bus requests (such as h(z) hold) while lock is active. this pin is configured as a weakly held high r(wh) input while resin is active and must not be driven low. p(1) 16
m80c186eb table 4. m80c186eb pin descriptions (continued) name type description hold i hold request input to signal that an external bus master wishes to gain control of the local bus. the m80c186eb will relinquish control of the local a(l) bus between instruction boundaries not conditioned by a lock prefix. hlda o hold acknowledge output to indicate that the m80c186eb has relinquish control of the local bus. when hlda is asserted, the m80c186eb will (or h(1) has) floated its data bus and control signals allowing another bus master to r(0) drive the signals directly. p(0) ncs o numerics coprocessor select output is generated when accessing a numerics coprocessor. h(1) r(1) p(1) error i error input that indicates the last numerics coprocessor operation resulted in an exception condition. an interrupt type 16 is generated if a(l) error is sampled active at the beginning of a numerics operation. pereq i coprocessor request signals that a data transfer between an external numerics coprocessor and memory is pending. a(l) ucs o upper chip select will go active whenever the address of a memory or i/o bus cycle is within the address limitations programmed by the user. after h(1) reset, ucs is configured to be active for memory accesses between r(1) 0ffc00h and 0fffffh. p(1) lcs o lower chip select will go active whenever the address of a memory bus cycle is within the address limitations programmed by the user. lcs is h(1) inactive after a reset. r(1) p(1) p1.0/gcs0 o these pins provide a multiplexed function. if enabled, each pin can provide a generic chip select output which will go active whenever the address of p1.1/gcs1 h(x)/h(1) a memory or i/o bus cycle is within the address limitations programmed by p1.2/gcs2 r(1) the user. when not programmed as a chip-select, each pin may be used as p1.3/gcs3 p(x)/p(1) a general purpose output port. as an output port pin, the value of the pin p1.4/gcs4 can be read internally. p1.5/gcs5 p1.6/gcs6 p1.7/gcs7 t0out o timer output pins can be programmed to provide a single clock or continuous waveform generation, depending on the timer mode selected. t1out h(q) r(1) p(q) t0in i timer input is used either as clock or control signals, depending on the timer mode selected. t1in a(l) a(e) 17
m80c186eb table 4. m80c186eb pin descriptions (continued) name type description int0 i maskable interrupt input will cause a vector to a specific type interrupt routine. to allow interrupt expansion, int0 and/or int1 can be used with int1 a(e,l) inta0 and inta1 to interface with an external slave controller. int4 int2/inta0 i/o these pins provide a multiplexed function. as inputs, they provide a maskable interrupt that will cause the cpu to vector to a specific type int3/inta1 a(e,l) interrupt routine. as outputs, each is programmatically controlled to provide /h(1) an interrupt acknowledge handshake signal to allow interrupt r(z) expansion. /p(1) p2.7 i/o bidirectional, open-drain port pins. p2.6 a(l) h(x) r(z) p(x) ctso i clear-to-send input is used to prevent the transmission of serial data on their respective txd signal pin. cts1 is multiplexed with an input only port p2.4/cts1 a(l) function. txd0 o transmit data output provides serial data information. txd1 is multiplexed with an output only port function. during synchronous serial p2.1/txd1 h(x)/h(q) communications, txd will function as a clock output. r(1) p(x)/p(q) rxd0 i/o receive data input accepts serial data information. rxd1 is multiplexed with an input only port function. during synchronous serial communications, p2.0/rxd1 a(l) rxd is bi-directional and will become an output for transmission or data r(z) (txd becomes the clock). h(q) p(x) p2.5/bclk0 i baud clock input can be used as an alternate clock source for each of the integrated serial channels. bclkx is multiplexed with an input only port p2.2/bclk1 a(l)/a(e) function, and cannot exceed a clock rate greater than one-half the operating frequency of the m80c186eb. p2.3/sint1 o serial interrupt output will go active to indicate serial channel 1 requires service. sint1 is multiplexed with an output only port function. h(x)/h(q) r(0) p(x)/p(q) 18
m80c186eb m80c186eb pinout table 5 lists the m80c186eb pin names with pack- age location for the 88-lead pin grid array (pga) component. figure 8 depicts the complete m80c186eb pinout as viewed from the bottom side of the component. table 5. mg80c186eb pin assignments plcc pga name 11 1a den 10 2b s0 91bs1 82cs2 7 1c bhe 6 2d ale 51dwr 42erd 3 1e error 22fv ss 11fv cc 84 2g v ss 83 1g a19/once 82 2h a18 81 1h a17 80 2j a16 79 1j ad15 78 2k ad7 77 1k ad14 76 2l ad6 75 1l ad13 e 2m n/c plcc pga name 74 1m ad5 73 1n ad12 72 2n ad4 71 3m ad11 70 3n ad3 69 4m ad10 68 4n ad2 67 5m ad9 66 5n ad1 65 6m v ss 64 6n v cc 63 7m v ss e 7n n/c 62 8m ad8 61 8n ad0 60 9m ncs 59 9n p2.2/bclk1 58 10m p2.1/txd1 57 10n p2.0/rxd1 56 11m p2.4/cts1 55 11n p2.3/sint1 54 12m p2.5/blck0 plcc pga name e 12n n/c 53 13n rxd0 52 13m txd0 51 12l cts0 50 13l p2.6 49 12k p2.7 48 13k t1in 47 12j t1out 46 13j t0in 45 12h t0out 44 13h clkout 43 12g v ss 42 13g v cc 41 12f clkin 40 13f oscout 39 12e pereq 38 13e resout 37 12d resin 36 13d pdtmr 35 12c int4 34 13c int3 33 12b int2 plcc pga name e 13b n/c 32 13a int1 31 12a int0 30 11b ucs 29 11a lcs 28 10b p1.0/gcs0 27 10a p1.1/gcs1 26 9b p1.2/gcs2 25 9a p1.3/gcs3 24 8b p1.4/gcs4 23 8a v cc 22 7b v ss 21 7a p1.5/gcs5 20 6b p1.6/gcs6 19 6a p1.7/gcs7 18 5b ready 17 5a nmi 16 4b drt/r 15 4a lock 14 3b test /busy 13 3a hold 12 2a hlda 19
m80c186eb pin grid array 271214 6 figure 8 20
m80c186eb electrical specifications absolute maximum ratings parameter maximum rating storage temperature b 65 cto a 150 c case temp under bias b 55 cto a 125 c supply voltage with respect to v ss b 0.5v to a 6.5v voltage on other pins with respect to v ss b 0.5v to v cc a 0.5v notice: this data sheet contains information on products in the sampling and initial production phases of development. it is valid for the devices indicated in the revision history. the specifications are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions symbol parameter min max units v cc supply voltage 4.5 5.5 v t f input clock frequency M80C186EB-16 0 32 mhz m80c186eb-13 0 26.08 mhz m80c186eb-8 0 16 mhz t c case temperature under bias b 55 a 125 c recommended connections power and ground connections must be made to multiple v cc and v ss pins. every m80c186eb- based circuit board should include separate power (v cc ) and ground (v ss ) planes. every v cc pin must be connected to the power plane, and every v ss pin must be connected to the ground plane. pins identi- fied as ``nc'' must not be connected in the system. liberal decoupling capacitance should be placed near the m80c186eb. the processor can cause transient power surges when its output buffers tran- sition, particularly when connected to large capaci- tive loads. low inductance capacitors and interconnects are recommended for best high frequency electrical per- formance. inductance is reduced by placing the de- coupling capacitors as close as possible to the m80c186eb v cc and v ss package pins. always connect any unused input to an appropriate signal level. in particular, unused interrupt inputs (int0:4) should be connected to v cc through a pull- up resistor (in the range of 50 k x ). leave any un- used output pin or any nc pin unconnected. 21
m80c186eb dc specifications symbol parameter min max units notes v il input low voltage b 0.5 0.3 * v cc v (note 8) v ih input high voltage 0.7 * v cc v cc a 0.5 v v ol output low voltage 0.45 v i ol e 3 ma (min) v oh output high voltage v cc b 0.5 v i oh eb 2 ma (min) v hyr input hysterisis on resin 0.50 v i li1 input leakage current for pins: ad15:0, ready, hold, resin , test , nmi, int4:0, t0in, t1in, rxd0, g 15 m a0v s v in s v cc bclk0 , cts0 , rxd1, bclk1 , cts1 , p2.6, p2.7 i li2 input leakage current for pin: clkin g 50 m a0v s v in s v cc i i1 input current for pin: error b 7 b 0.275 ma v in e 0v i i2 input current for pin: pereq a 0.275 a 7mav in e v cc i lo output leakage current g 15 m a 0.45 s v out s v cc (notes 2, 7) i cc supply current cold (reset) M80C186EB-16 90 ma (note 3) m80c186eb-13 73 ma (note 3) m80c186eb-8 45 ma (note 3) i id supply current idle M80C186EB-16 63 ma (note 4) m80c186eb-13 48 ma (note 4) m80c186eb-8 31 ma (note 4) i pd supply current powerdown M80C186EB-16 100 m a (note 5) m80c186eb-13 100 m a (note 5) m80c186eb-8 100 m a (note 5) cin input pin capacitance 0 15 pf t f e 1 mhz cout output pin capacitance 0 15 pf t f e 1 mhz (note 6) notes: 1. these pins have an internal pull-up device that is active while resin is low and once mode is not active. sourcing more current than specified (on any of these pins) may invoke a factory test mode. 2. tested by outputs being floated by invoking once mode or by asserting hold. 3. measured with the device in reset and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 4. measured with the device in halt (idle mode active) and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 5. measured with the device in halt (powerdown mode active) and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 6. output capacitance is the capacitive load of a floating output pin. 7. osc out is not tested. 8. a19/once , a18:16, lock are not tested. 22
m80c186eb i cc versus frequency and voltage the current (i cc ) consumption of the m80c186eb is essentially composed of two components; i pd and i ccs . i pd is the quiescent current that represents internal device leakage, and is measured with all inputs or floating outputs at gnd or v cc (no clock applied to the device). i pd is equal to the powerdown current and is typically less than 50 m a. i ccs is the switching current used to charge and discharge parasitic device capacitance when chang- ing logic levels. since i ccs is typically much greater than i pd ,i pd can often be ignored when calculating i cc . i ccs is related to the voltage and frequency at which the device is operating. it is given by the formula: power e v c i e v 2 c c dev c f . . . i e i cc e i ccs e v c c dev c f where: v e device operating voltage (v cc ) c dev e device capacitance f e device operating frequency i ccs e i cc e device current measuring c dev on a device like the m80c186eb would be difficult. instead, c dev is calculated using the above formula by measuring i cc at a known v cc and frequency (see table 11). using this c dev val- ue, i cc can be calculated at any voltage and fre- quency within the specified operating range. example: calculate the typical i cc when operating at 10 mhz, 4.8v. i cc e i ccs e 4.8 c 0.583 c 10 & 28 ma pdtmr pin delay calculation the pdtmr pin provides a delay between the as- sertion of nmi and the enabling of the internal clocks when exiting powerdown. a delay is required only when using the on-chip oscillator to allow the crystal or resonator circuit time to stabilize. note: the pdtmr pin function does not apply when resin is asserted (i.e., a device reset during pow- erdown is similar to a cold reset and resin must remain active until after the oscillator has stabi- lized). to calculate the value of capacitor required to pro- vide a desired delay, use the equation: 440 c t e c pd (5v, 25 c) where: t e desired delay in seconds c pd e capacitive load on pdtmr in mi- crofarads example: to get a delay of 300 m s, a capacitor value of c pd e 440 c (300 c 10 b 6 ) e 0.132 m fis required. round up to standard (available) capaci- tive values. note: the above equation applies to delay times greater than 10 m s and will compute the typical capaci- tance needed to achieve the desired delay. a delay variance of a 50% or b 25% can occur due to temperature, voltage, and device process ex- tremes. in general, higher v cc and/or lower tem- perature will decrease delay time, while lower v cc and/or higher temperature will increase delay time. table 11. device capacitance (c dev ) values parameter typ max units notes c dev (device in reset) 0.583 1.02 ma/v * mhz 1, 2 c dev (device in idle) 0.408 0.682 ma/v * mhz 1, 2 1. max c dev is calculated at b 40 c, all floating outputs driven to v cc or gnd, and all outputs loaded to 50 pf (including clkout and oscout). 2. typical c dev is calculated at 25 c with all outputs loaded to 50 pf except clkout and oscout, which are not loaded. 23
m80c186eb ac specifications ac characteristicseM80C186EB-16 symbol parameter min max units notes input clock t f clkin frequency 0 32 mhz 1 t c clkin period 31.25 % ns 1 t ch clkin high time 10 % ns 1, 2 t cl clkin low time 10 % ns 1, 2 t cr clkin rise time 1 8 ns 1, 3, 11 t cf clkin fall time 1 8 ns 1, 3, 11 output clock t cd clkin to clkout delay 0 20 ns 1, 4 t clkout period 2 * t c ns 1 t ph clkout high time (t/2) b 5 (t/2) a 5ns 1 t pl clkout low time (t/2) b 5 (t/2) a 5ns 1 t pr clkout rise time 6 ns 1, 5 t pf clkout fall time 6 ns 1, 5 output delays t chov1 ale, s2:0 , den , dt/r , bhe , 1 22 ns 1, 4, 6, 7 lock , a19:16 t chov2 gcs0:7 , lcs , ucs , ncs ,rd ,wr 1 27 ns 1,4,6,8 t clov1 bhe , den , lock , resout, hlda, 1 22 ns 1, 4, 6 t0out, t1out, a19:16 t clov2 rd ,wr , gcs7:0 , lcs , ucs , 1 27 ns 1, 4, 6 ad15:0, ncs , inta1:0 , s2:0 t chof rd ,wr , bhe , dt/r , 0 25 ns 1, 11 lock , s2:0 , a19:16 t clof den , ad15:0 0 25 ns 1, 11 synchronous inputs t chis test , nmi, int4:0, bclk1:0, 10 ns 1, 9 t1:0in, ready, cts1:0 , p2.6, p2.7 t chih test , nmi, int4:0, bclk1:0, 3 ns 1, 9 t1:0in, ready, cts1:0 t clis ad15:0, ready 10 ns 1, 10 t clih ready, ad15:0 3 ns 1, 10 t clis hold, pereq, error 10 ns 1, 9 t clih hold, pereq, error 3ns1,9 notes: 1. see ac timing waveforms , for waveforms and definition. 2. measure at v ih for high time, v il for low time. 3. only required to guarantee i cc . maximum limits are bounded by t c ,t ch and t cl . 4. specified for a 50 pf load, see figure 16 for capacitive derating information. 5. specified for a 50 pf load, see figure 17 for rise and fall times outside 50 pf. 6. see figure 17 for rise and fall times. 7. t chov1 applies to bhe , lock and a19:16 only after a hold release. 8. t chov2 applies to rd and wr only after a hold release. 9. setup and hold are required to guarantee recognition. 10. setup and hold are required for proper m80c186eb operation. 11. not tested. 24
m80c186eb ac specifications ac characteristicsem80c186eb-13 symbol parameter min max units notes input clock t f clkin frequency 0 26.08 mhz 1 t c clkin period 38.34 % ns 1 t ch clkin high time 12 % ns 1, 2 t cl clkin low time 12 % ns 1, 2 t cr clkin rise time 1 8 ns 1, 3 t cf clkin fall time 1 8 ns 1, 3 output clock t cd clkin to clkout delay 0 23 ns 1, 4 t clkout period 2 * t c ns 1 t ph clkout high time (t/2) b 5 (t/2) a 5ns 1 t pl clkout low time (t/2) b 5 (t/2) a 5ns 1 t pr clkout rise time 6 ns 1, 5 t pf clkout fall time 6 ns 1, 5 output delays t chov1 ale, s2:0 , den , dt/r , bhe , 1 25 ns 1, 4, 6, 7 lock , a19:16 t chov2 gcs0:7 , lcs , ucs , ncs ,rd ,wr 1 30 ns 1,4,6,8 t clov1 bhe , den , lock , resout, hlda, 1 25 ns 1, 4, 6 t0out, t1out, a19:16 t clov2 rd ,wr , gcs7:0 , lcs , ucs , 1 30 ns 1, 4, 6 ad15:0, ncs , inta1:0 , s2:0 t chof rd ,wr , bhe , dt/r , 0 25 ns 1, 11 lock , s2:0 , a19:16 t clof den , ad15:0 0 25 ns 1, 11 synchronous inputs t chis test , nmi, int4:0, bclk1:0, 10 ns 1, 9 t1:0in, ready, cts1:0 , p2.6, p2.7 t chih test , nmi, int4:0, bclk1:0, 3 ns 1, 9 t1:0in, ready, cts1:0 t clis ad15:0, ready 10 ns 1, 10 t clih ready, ad15:0 3 ns 1, 10 t clis hold, pereq, error 10 ns 1, 9 t clih hold, pereq, error 3ns1,9 notes: 1. see ac timing waveforms , for waveforms and definition. 2. measure at v ih for high time, v il for low time. 3. only required to guarantee i cc . maximum limits are bounded by t c ,t ch and t cl . 4. specified for a 50 pf load, see figure 16 for capacitive derating information. 5. specified for a 50 pf load, see figure 17 for rise and fall times outside 50 pf. 6. see figure 17 for rise and fall times. 7. t chov1 applies to bhe , lock and a19:16 only after a hold release. 8. t chov2 applies to rd and wr only after a hold release. 9. setup and hold are required to guarantee recognition. 10. setup and hold are required for proper m80c186eb operation. 11. not tested. 25
m80c186eb ac characteristicsem80c186eb-8 symbol parameter min max units notes input clock t f clkin frequency 0 16 mhz 1 t c clkin period 62.5 % ns 1 t ch clkin high time 15 % ns 1, 2 t cl clkin low time 15 % ns 1, 2 t cr clkin rise time 1 8 ns 1, 3 t cf clkin fall time 1 8 ns 1, 3 output clock t cd clkin to clkout delay 0 27 ns 1, 4 t clkout period 2 * t c ns 1 t ph clkout high time (t/2) b 5 (t/2) a 5ns 1 t pl clkout low time (t/2) b 5 (t/2) a 5ns 1 t pr clkout rise time 6 ns 1, 5 t pf clkout fall time 6 ns 1, 5 output delays t chov1 ale, s2:0 , den , dt/r , bhe , 1 30 ns 1, 4, 6, 7 lock , a19:16 t chov2 gcs0:7 , lcs , ucs , ncs ,rd ,wr 1 35 ns 1,4,6,8 t clov1 bhe , den , lock , resout, hlda, 1 30 ns 1, 4, 6 t0out, t1out, a19:16 t clov2 rd ,wr , gcs7:0 , lcs , ucs , 1 35 ns 1, 4, 6 ad15:0, ncs , inta1:0 , s2:0 t chof rd ,wr , bhe , dt/r , 0 30 ns 1, 11 lock , s2:0 , a19:16 t clof den , ad15:0 0 35 ns 1, 11 synchronous inputs t chis test , nmi, int4:0, bclk1:0, 10 ns 1, 9 t1:0in, ready, cts1:0 , p2.6, p2.7 t chih test , nmi, int4:0, bclk1:0, 3 ns 1, 9 t1:0in, ready, cts1:0 t clis ad15:0, ready 10 ns 1, 10 t clih ready, ad15:0 3 ns 1, 10 t clis hold, pereq, error 10 ns 1, 9 t clih hold, pereq, error 3ns1,9 notes: 1. see ac timing waveforms , for waveforms and definition. 2. measure at v ih for high time, v il for low time. 3. only required to guarantee i cc . maximum limits are bounded by t c ,t ch and t cl . 4. specified for a 50 pf load, see figure 16 for capacitive derating information. 5. specified for a 50 pf load, see figure 17 for rise and fall times outside 50 pf. 6. see figure 17 for rise and fall times. 7. t chov1 applies to bhe , lock and a19:16 only after a hold release. 8. t chov2 applies to rd and wr only after a hold release. 9. setup and hold are required to guarantee recognition. 10. setup and hold are required for proper m80c186eb operation. 11. not tested. 26
m80c186eb relative timings (M80C186EB-16, -13, -8) symbol parameter min max unit notes relative timings t lhll ale rising to ale falling t b 15 ns t avll address valid to ale falling (/2 t b 10 ns t plll chip selects valid to ale falling (/2 t b 10 ns 1 t llax address hold from ale falling (/2 t b 10 ns t llwl ale falling to wr falling (/2 t b 15 ns 1 t llrl ale falling to rd falling (/2 t b 15 ns 1 t whlh wr rising to ale rising (/2 t b 10 ns 1 t afrl address float to rd falling 0 ns t rlrh rd falling to rd rising (2 * t) b 5ns2 t wlwh wr falling to wr rising (2 * t) b 5ns2 t rhav rd rising to address active t b 15 ns t whdx output data hold after wr rising t b 15 ns t whph wr rising to chip select rising (/2 t b 10 ns 1 t rhph rd rising to chip select rising (/2 t b 10 ns 1 t phpl cs inactive to cs active (/2 t b 10 ns 1 t ovrh once active to resin rising t ns 3 t rhox once hold from resin rising t ns 3 notes: 1. assumes equal loading on both pins. 2. can be extended using wait states. 3. not tested. 27
m80c186eb serial port mode 0 timings (M80C186EB-16, -13, -8) symbol parameter min max unit notes t xlxl txd clock period t (n a 1) ns 1, 2 t xlxh txd clock low to clock high (n l 1) 2t b 35 2t a 35 ns 1 t xlxh txd clock low to clock high (n e 1) t b 35 t a 35 ns 1 t xhxl txd clock high to clock low (n l 1) (n b 1) t b 35 (n b 1) t a 35 ns 1, 2 t xhxl txd clock high to clock low (n e 1) t b 35 t a 35 ns 1 t qvxh rxd output data setup to txd clock high (n l 1) (n b 1) t b 35 ns 1, 2 t qvxh rxd output data setup to txd clock high (n e 1) t b 35 ns 1 t xhqx rxd output data hold after txd clock high (n l 1) 2t b 35 ns 1 t xhqx rxd output data hold after txd clock high (n e 1) t b 35 ns 1 t xhqz rxd output data float after last txd clock high t a 20 ns 1, 3 t dvxh rxd input data setup to txd clock high t a 20 ns 1 t xhdx rxd input data hold after txd clock high 0 ns 1, 3 notes: 1. see figure 14 for waveforms. 2. n is the value of the bxcmp register ignoring the iclk bit (i.e., iclk e 0). 3. guaranteed, not tested. 28
m80c186eb ac test conditions the ac specifications are tested with the 50 pf load shown in figure 9. see the derating curves section to see how timings vary with load capacitance. specifications are measured at the v cc /2 crossing point, unless otherwise specified. see ac timing waveforms, for ac specification definitions, test pins, and illustrations. 271214 7 c l e 50 pf for all signals. figure 9. ac test load ac timing waveforms 271214 8 figure 10. input and output clock waveform 29
m80c186eb 271214 9 note: 20% v cc k float k 80% v cc figure 11. output delay and float waveform 271214 10 figure 12. input setup and hold 30
m80c186eb 271214 11 figure 13. relative signal waveform 271214 12 figure 14. serial port mode 0 waveform 31
m80c186eb derating curves typical output delay variations versus load capacitance 271214 13 figure 15 typical rise and fall variations versus load capacitance 271214 14 figure 16 32
m80c186eb reset the m80c186eb will perform a reset operation any time the resin pin active. the resin pin is actually synchronized before it is presented internally, which means that the clock must be operating before a reset can take effect. from a power-on state, resin must be held active (low) in order to guarantee cor- rect initialization of the m80c186eb. failure to pro- vide resin while the device is powering up will result in unspecified operation of the device. figure 17 shows the correct reset sequence when first applying power to the m80c186eb. an external clock connected to clkin must not exceed the v cc threshold being applied to the m80c186eb. this is normally not a problem if the clock driver is supplied with the same v cc that supplies the m80c186eb. when attaching a crystal to the device, resin must remain active until both v cc and clkout are stable (the length of time is application specific and de- pends on the startup characteristics of the crystal circuit). the resin pin is designed to operate cor- rectly using an rc reset circuit, but the designer must ensure that the ramp time for v cc is not so long that resin is never really sampled at a logic low level when v cc reaches minimum operating conditions. figure 18 shows the timing sequence when resin is applied after v cc is stable and the device has been operating. note that a reset will terminate all activity and return the m80c186eb to a known oper- ating state. any bus operation that is in progress at the time resin is asserted will terminate immediate- ly (note that most control signals will be driven to their inactive state first before floating). while resin is active, bus signals lock , a19/ once , and a18:16 are configured as inputs and weakly held high by internal pullup transistors. only 19/once can be overdriven to a low and is used to enable once mode. forcing lock or a18:16 low at any time while resin is low is prohibited and will cause unspecified device operation. 33
m80c186eb cold reset waveforms figure 17 271214 15 note: clkout synchronization occurs on the rising edge of resin . if resin is sampled high while clkout is high (solid line), then clkout will remain low for two clkin periods. if resin is sampled high while clkout is low (dashed line), then clkout will not be affected. 34
m80c186eb warm reset waveforms figure 18 271214 16 35
m80c186eb bus cycle waveforms figures 19 through 25 present the various bus cy- cles that are generated by the m80c186eb. what is shown in the figure is the relationship of the various bus signals to clkout. these figures along with the information present in ac specifications allow the user to determine all the critical timing analysis needed for a given application. figure 19 shows the m80c186eb bus state diagram. a typical bus cycle will consist of four consecutive states labeled t1, t2, t3 and t4. a ti state exists when no bus cycle is pending. a ti state can occur if the pre-fetch queue is full, the biu is waiting for the completion of an effective address calculation, or the biu is told to wait for a pending eu bus opera- tion. the latter case will occur most often during the sequencing of an interrupt acknowledge or during the execution of numerics escape instructions. aside from ti states, multiple t3 states can occur during a bus cycle if ready is not returned in time (or the csu has been programmed to automatically insert wait-states). a t3 state will be followed by ei- ther a t4 state (if a bus cycle is pending), or a ti state (if no bus cycle is pending). only multiple t3 or ti states can exist (i.e., there is no way to extend the t1, t2 or t4 states). figures 20 and 21 present a typical bus read and write operation respectively. bus read operations in- clude memory, i/o, instruction fetch, and refresh bus cycles. bus write operations include memory and i/o bus cycles. the only variation among the different bus cycles would be the range of address generated and the state of the status signals. the halt bus cycle is shown in figure 22. note that the condition of the ad15:0 pin can be either floating or driving depending on the operation of the bus cy- cle that preceded the halt. the pins will float if the previous bus cycle was a read, otherwise they will drive. none of the control signals (e.g., rd ,wr , den , etc.) will be activated, however. figure 23 shows the sequence of bus cycles run when an interrupt is acknowledged and the icu has been programmed for cascade mode. note the ad- dress information is not valid for the two bus cycles run, however, also note that rd and wr are not generated. vector information needs to be returned during the second bus cycle. figures 24 and 25 present the operation of bus hold. figure 24 shows how bus hold is entered and exited under normal operating conditions. fig- ure 25 shows the effect specific bus signals have when a refresh bus cycle request has been generat- ed and the bus is currently unavailable due to a bus hold. the effects of ready on bus operation is shown in figure 26. ready is useful in extending the bus cy- cle to meet the various access requirements for memory and peripheral devices in the system. addi- tional t3 states added to the bus cycle have been appropriately labeled tw. 271214 17 figure 19. m80c186eb bus states 36
m80c186eb memory read, i/o read, instruction fetch and refresh waveform 271214 18 figure 20 37
m80c186eb memory write and i/o write cycle waveform 271214 19 figure 21 38
m80c186eb halt cycle waveform 271214 20 note: the address driven is typically the location of the next instruction prefetch. under a majority of instruction sequences the ad15:0 bus will float, while the a19:16 bus remains driven and all bus control signals are driven to their inactive state. figure 22 39
m80c186eb cascade mode interrupt acknowledge cycle waveform 271214 21 figure 23 40
m80c186eb hold/hlda cycle waveforms 271214 22 figure 24 41
m80c186eb refresh during hlda cycle waveform 271214 23 notes: 1. ready must be low by either edge to cause a wait state. 2. lighter lines indicate read cycles, darker lines indicate write cycles. figure 25 42
m80c186eb ready cycle waveform 271214 24 notes: 1. ready must be low by either edge to cause a wait state. 2. lighter lines indicate read cycles, darker lines indicate write cycles. figure 26 43
m80c186eb register bit summary figures 27 through 34 present the bit definition of each register that is active (not reserved) in the pe- ripheral control block (pcb). each register can be thought to occupy one word (16-bits) of either mem- ory or i/o space, although not all bits in the register necessarily have a function. a register bit is not guaranteed to return a specific logic value if an ``x'' appears for the bit definition (i.e., if a zero was writ- ten to the register bit it may not be returned as a zero when read). furthermore , a 0 must be written to any bit that is indicated by an ``x'' to ensure compati- bility with future products or potential product chang- es. not all defined register bits can be read and/or written, although most registers are read/write. some registers, like the p1dir register, exist but do not have any effect on the operation of the m80c186eb. for example, the port1 pins are output only and cannot be changed by programming the p1dir register. however, the p1dir register can still be read and writtenewhich allows the p1dir regis- ter to be used as a temporary 8-bit data register. reads and writes to any of the pcb registers will cause a bus cycle to be run externally, however, none of the chip selects will go active (even if they overlap the pcb address range). data read back from the ad15:0 bus is ignored, and all cycles will take zero wait states (except accesses to the timer/ counter registers which take one wait state due to internal synchronization). figures 27 and 28 present the registers associated with the interrupt control unit (icu). a write to the mask (08h) register will also effect the correspond- ing msk bit in each of the control registers (e.g., setting the tmr bit in the mask register will also set the msk bit in the tmrcon register). the timer/counter unit registers are presented in figure 29. the compare and count registers are not initialized after reset and must be set correctly dur- ing initialization to ensure the timer operates correct- ly the first time it is enabled. figure 30 presents the i/o port unit (ipu) registers. only pd6 and pd7 or of the p2dir register have any effect on the direction of the port pins (p2.6 and p2.7 respectively). the unused bits of p2dir and all the bits of p1dir can be thought of having latches that can be read and written. the two pxltch regis- ters have all 8-bits implemented, however, only those port pins which can function as outputs actual- ly use the value programmed into the latch. other- wise (like the p1dir register), the registers can be thought of being an 8-bit data register. figure 31 presents the register bit definitions of the serial communications unit (scu). the transmit and receive buffer registers are both readable and write- able. note that a read from sxsts register will clear all of the status information (except for cts, which actually is derived from the pin itself). the chip-select unit (csu) registers are presented in figure 32 and the refresh control unit (rcu) reg- isters are presented in figure 33. the rfaddr reg- ister will indicate the current refresh address when read, and a write to the register will change the next refresh address generated. figure 34 presents the pwrcon register and stepid register. the stepid register contains a stepping identifier that may or may not change any time there is a change to the m80c186eb silicon die. the stepid is for intel use and can change at any time. 44
m80c186eb 271214 25 figure 27. interrupt control unit registers 271214 26 figure 28. interrupt control unit registers 45
m80c186eb 271214 27 figure 29. timer control unit registers 271214 28 figure 30. i/o port unit registers 46
m80c186eb 271214 29 figure 31. serial communications unit registers 271214 30 figure 32. chip-select unit registers 47
m80c186eb 271214 31 figure 33. refresh control unit registers 271214 32 figure 34. power management unit registers m80c186eb execution timings a determination of m80c186eb program execution timing must consider the bus cycles necessary to prefetch instructions as well as the number of exe- cution unit cycles necessary to execute instructions. the following instruction timings represent the mini- mum execution time in clock cycles for each instruc- tion. the timings given are based on the following assumptions: # the opcode, along with any data or displacement required for execution of a particular instruction, has been prefetched and resides in the queue at the time it is needed. # no wait states or bus holds occur. # all word-data is located on even-address bound- aries. all jumps and calls include the time required to fetch the opcode of the next instruction at the destination address. all instructions which involve memory accesses can require one or two additional clocks above the mini- mum timings shown due to the asynchronous hand- shake between the bus interface unit (biu) and exe- cution unit. with a 16-bit biu, the m80c186eb has sufficient bus performance to ensure that an adequate number of prefetched bytes will reside in the queue most of the time. therefore, actual program execution time will not be substantially greater than that derived from adding the instruction timings shown. 48
m80c186eb instruction set summary function format clock comments cycles data transfer mov e move: register to register/memory 1000100w modreg r/m 2/12 register/memory to register 1000101w modreg r/m 2/9 immediate to register/memory 1100011w mod000 r/m data data if w e 1 12 13 8/16-bit immediate to register 1011w reg data data if w e 1 3 4 8/16-bit memory to accumulator 1010000w addr-low addr-high 8 accumulator to memory 1010001w addr-low addr-high 9 register/memory to segment register 10001110 mod0reg r/m 2/9 segment register to register/memory 10001100 mod0reg r/m 2/11 push e push: memory 11111111 mod110 r/m 16 register 01010 reg 10 segment register 000reg110 9 immediate 011010s0 data data if s e 010 pusha e push all 01100000 36 pop e pop: memory 10001111 mod000 r/m 20 register 01011 reg 10 segment register 000reg111 (reg i 01) 8 popa e popall 01100001 51 xchg e exchange: register/memory with register 1000011w modreg r/m 4/17 register with accumulator 10010 reg 3 in e input from: fixed port 1110010w port 10 variable port 1110110w 8 out e output to: fixed port 1110011w port 9 variable port 1110111w 7 xlat e translate byte to al 11010111 11 lea e load ea to register 10001101 modreg r/m 6 lds e load pointer to ds 11000101 modreg r/m (mod i 11) 18 les e load pointer to es 11000100 modreg r/m (mod i 11) 18 lahf e load ah with flags 10011111 2 sahf e store ah into flags 10011110 3 pushf e push flags 10011100 9 popf e pop flags 10011101 8 shaded areas indicate instructions not available in m8086/m8088 microsystems. 49
m80c186eb instruction set summary (continued) function format clock comments cycles data transfer (continued) segment e segment override: cs 00101110 2 ss 00110110 2 ds 00111110 2 es 00100110 2 arithmetic add e add: reg/memory with register to either 000000dw modreg r/m 3/10 immediate to register/memory 100000sw mod000 r/m data data if s w e 01 4/16 immediate to accumulator 0000010w data data if w e 1 3/4 8/16-bit adc e add with carry: reg/memory with register to either 000100dw modreg r/m 3/10 immediate to register/memory 100000sw mod010 r/m data data if s w e 01 4/16 immediate to accumulator 0001010w data data if w e 1 3/4 8/16-bit inc e increment: register/memory 1111111w mod000 r/m 3/15 register 01000 reg 3 sub e subtract: reg/memory and register to either 001010dw modreg r/m 3/10 immediate from register/memory 100000sw mod101 r/m data data if s w e 01 4/16 immediate from accumulator 0010110w data data if w e 1 3/4 8/16-bit sbb e subtract with borrow: reg/memory and register to either 000110dw modreg r/m 3/10 immediate from register/memory 100000sw mod011 r/m data data if s w e 01 4/16 immediate from accumulator 0001110w data data if w e 1 3/4 8/16-bit dec e decrement register/memory 1111111w mod001 r/m 3/15 register 01001 reg 3 cmp e compare: register/memory with register 0011101w modreg r/m 3/10 register with register/memory 0011100w modreg r/m 3/10 immediate with register/memory 100000sw mod111 r/m data data if s w e 01 3/10 immediate with accumulator 0011110w data data if w e 1 3/4 8/16-bit neg e change sign register/memory 1111011w mod011 r/m 3/10 aaa e ascii adjust for add 00110111 8 daa e decimal adjust for add 00100111 4 aas e ascii adjust for subtract 00111111 7 das e decimal adjust for subtract 00101111 4 mul e multiply (unsigned): 1111011w mod100 r/m register-byte 2628 register-word 3537 memory-byte 3234 memory-word 4143 shaded areas indicate instructions not available in m8086/m8088 microsystems. 50
m80c186eb instruction set summary (continued) function format clock comments cycles arithmetic (continued) imul e integer multiply (signed): 1111011w mod101 r/m register-byte 2528 register-word 3437 memory-byte 3134 memory-word 4043 imul e integer immediate multiply 011010s1 modreg r/m data data if s e 0 22 25/ (signed) 2932 div e divide (unsigned): 1111011w mod110 r/m register-byte 29 register-word 38 memory-byte 35 memory-word 44 idiv e integer divide (signed): 1111011w mod111 r/m register-byte 4452 register-word 5361 memory-byte 5058 memory-word 5967 aam e ascii adjust for multiply 11010100 00001010 19 aad e ascii adjust for divide 11010101 00001010 15 cbw e convert byte to word 10011000 2 cwd e convert word to double word 10011001 4 logic shift/rotate instructions: register/memory by 1 1101000w modtttr/m 2/15 register/memory by cl 1101001w modtttr/m 5 a n/17 a n register/memory by count 1100000w modtttr/m count 5 a n/17 a n ttt instruction 000 rol 001 ror 010 rcl 011 rcr 1 0 0 shl/sal 101 shr 111 sar and e and: reg/memory and register to either 001000dw modreg r/m 3/10 immediate to register/memory 1000000w mod100 r/m data data if w e 1 4/16 immediate to accumulator 0010010w data data if w e 1 3/4 8/16-bit test e and function to flags, no result: register/memory and register 1000010w modreg r/m 3/10 immediate data and register/memory 1111011w mod000 r/m data data if w e 1 4/10 immediate data and accumulator 1010100w data data if w e 1 3/4 8/16-bit or e or: reg/memory and register to either 000010dw modreg r/m 3/10 immediate to register/memory 1000000w mod001 r/m data data if w e 1 4/16 immediate to accumulator 0000110w data data if w e 1 3/4 8/16-bit shaded areas indicate instructions not available in m8086/m8088 microsystems. 51
m80c186eb instruction set summary (continued) function format clock comments cycles logic (continued) xor e exclusive or: reg/memory and register to either 001100dw modreg r/m 3/10 immediate to register/memory 1000000w mod110 r/m data data if w e 1 4/16 immediate to accumulator 0011010w data data if w e 1 3/4 8/16-bit not e invert register/memory 1111011w mod010 r/m 3/10 string manipulation movs e move byte/word 1010010w 14 cmps e compare byte/word 1010011w 22 scas e scan byte/word 1010111w 15 lods e load byte/wd to al/ax 1010110w 12 stos e store byte/wd from al/ax 1010101w 10 ins e input byte/wd from dx port 0110110w 14 outs e output byte/wd to dx port 0110111w 14 repeated by count in cx (rep/repe/repz/repne/repnz) movs e move string 11110010 1010010w 8 a 8n cmps e compare string 1111001z 1010011w 5 a 22n scas e scan string 1111001z 1010111w 5 a 15n lods e load string 11110010 1010110w 6 a 11n stos e store string 11110010 1010101w 6 a 9n ins e input string 11110010 0110110w 8 a 8n outs e output string 11110010 0110111w 8 a 8n control transfer call e call: direct within segment 11101000 disp-low disp-high 15 register/memory 11111111 mod010 r/m 13/19 indirect within segment direct intersegment 10011010 segment offset 23 segment selector indirect intersegment 11111111 mod011 r/m (mod i 11) 38 jmp e unconditional jump: short/long 11101011 disp-low 14 direct within segment 11101001 disp-low disp-high 14 register/memory 11111111 mod100 r/m 11/17 indirect within segment direct intersegment 11101010 segment offset 14 segment selector indirect intersegment 11111111 mod101 r/m (mod i 11) 26 shaded areas indicate instructions not available in m8086/m8088 microsystems. 52
m80c186eb instruction set summary (continued) function format clock comments cycles control transfer (continued) ret e return from call: within segment 11000011 16 within seg adding immed to sp 11000010 data-low data-high 18 intersegment 11001011 22 intersegment adding immediate to sp 11001010 data-low data-high 25 je/jz e jump on equal/zero 01110100 disp 4/13 jmp not jl/jnge e jump on less/not greater or equal 01111100 disp 4/13 taken/jmp jle/jng e jump on less or equal/not greater 01111110 disp 4/13 taken jb/jnae e jump on below/not above or equal 01110010 disp 4/13 jbe/jna e jump on below or equal/not above 01110110 disp 4/13 jp/jpe e jump on parity/parity even 01111010 disp 4/13 jo e jump on overflow 01110 000 disp 4/13 js e jump on sign 01111000 disp 4/13 jne/jnz e jump on not equal/not zero 01110101 disp 4/13 jnl/jge e jump on not less/greater or equal 01111101 disp 4/13 jnle/jg e jump on not less or equal/greater 01111111 disp 4/13 jnb/jae e jump on not below/above or equal 01110011 disp 4/13 jnbe/ja e jump on not below or equal/above 01110111 disp 4/13 jnp/jpo e jump on not par/par odd 01111011 disp 4/13 jno e jump on not overflow 01110001 disp 4/13 jns e jump on not sign 01111001 disp 4/13 jcxz e jump on cx zero 11100011 disp 5/15 loop e loop cx times 11100010 disp 6/16 loop not loopz/loope e loop while zero/equal 11100001 disp 6/16 taken/loop loopnz/loopne e loop while not zero/equal 11100000 disp 6/16 taken enter e enter procedure 11001000 data-low data-high l l e 0 15 l e 1 25 l l 1 22 a 16(n b 1) leave e leave procedure 11001001 8 int e interrupt: type specified 11001101 type 47 type 3 11001100 45 if int. taken/ into e interrupt on overflow 11001110 48/4 if int. not taken iret e interrupt return 11001111 28 bound e detect value out of range 01100010 modreg r/m 3335 shaded areas indicate instructions not available in m8086/m8088 microsystems. 53
m80c186eb instruction set summary (continued) function format clock comments cycles processor control clc e clear carry 11111000 2 cmc e complement carry 11110101 2 stc e set carry 11111001 2 cld e clear direction 11111100 2 std e set direction 11111101 2 cli e clear interrupt 11111010 2 sti e set interrupt 11111011 2 hlt e halt 11110100 2 wait e wait 10011011 6 if test e 0 lock e bus lock prefix 11110000 2 nop e no operation 10010000 3 (ttt lll are opcode to processor extension) shaded areas indicate instructions not available in m8086/m8088 microsystems. footnotes the effective address (ea) of the memory operand is computed according to the mod and r/m fields: if mod e 11 then r/m is treated as a reg field if mod e 00 then disp e 0 * , disp-low and disp- high are absent if mod e 01 then disp e disp-low sign-ex- tended to 16-bits, disp-high is absent if mod e 10 then disp e disp-high: disp-low if r/m e 000 then ea e (bx) a (si) a disp if r/m e 001 then ea e (bx) a (di) a disp if r/m e 010 then ea e (bp) a (si) a disp if r/m e 011 then ea e (bp) a (di) a disp if r/m e 100 then ea e (si) a disp if r/m e 101 then ea e (di) a disp if r/m e 110 then ea e (bp) a disp * if r/m e 111 then ea e (bx) a disp disp follows 2nd byte of instruction (before data if required) * except if mod e 00 and r/m e 110 then ea e disp-high: disp-low. ea calculation time is 4 clock cycles for all modes, and is included in the execution times given whenev- er appropriate. segment override prefix 0 0 1 reg 1 1 0 reg is assigned according to the following: segment reg register 00 es 01 cs 10 ss 11 ds reg is assigned according to the following table: 16-bit (w e 1) 8-bit (w e 0) 000 ax 000 al 001 cx 001 cl 010 dx 010 dl 011 bx 011 bl 100 sp 100 ah 101 bp 101 ch 110 si 110 dh 111 di 111 bh the physical addresses of all operands addressed by the bp register are computed using the ss seg- ment register. the physical addresses of the desti- nation operands of the string primitive operations (those addressed by the di register) are computed using the es segment, which may not be overridden. 54
m80c186eb 88-lead ceramic pin grid array package 271214 33 family: ceramic pin grid array package symbol millimeters inches min max notes min max notes a 3.56 4.57 0.140 0.180 a 1 0.76 1.27 solid lid 0.030 0.050 solid lid a 2 2.67 3.43 solid lid 0.105 0.135 solid lid a 3 1.14 1.40 0.045 0.055 b 0.43 0.51 0.017 0.020 d 33.91 34.67 1.335 1.365 d 1 30.35 30.61 1.195 1.205 e 1 2.29 2.79 0.090 0.110 l 2.54 3.30 0.100 0.130 n88 88 s 1 1.27 2.54 0.050 0.100 issue iws 10/12/88 55
m80c186eb errata the current stepping (b step) of the m80c186eb has the following known functional anomaly. an internal problem with the interrupt controller may prevent an acknowledge cycle from occur- ring on the inta1 line after an interrupt on int1. this error only occurs when int1 is configured in cascaded mode and a higher priority interrupt ex- ists. problem: an interrupt acknowledge for int1 is not generat- ed on inta1 in some conditions. condition: another interrupt of higher priority occurs after the decision is made to service interrupt 1, but before the expected acknowledge cycle on inta1. configuration: 1. master mode 2. int1 is in cascade mode and is enabled. 3. an interrupt of higher priority than int1 is en- abled (i.e., dma, timers, serial ports, int lines). workaround: there are only two possible situations that might cause this problem. these, with their correspond- ing workarounds are described in the table below. condition workaround 1. only int1 is use int0 in cascaded configured in cascade mode instead, or mode and is also a make int1 the highest lower priority than priority interrupt. another interrupt. 2. int1 and int0 are change the priority of both in cascade mode int1 to the highest and int1 is of lower priority of all interrupts. priority than another interrupt. revision history the first revision of this data sheet (271214-001) in- dicated only 8 mhz and 13 mhz availability. the m80c186eb will also be available in a 16 mhz ver- sion. the cover and various other locations in the data sheet reflect the additional product speed offer- ing. the following list reflects the changes made be- tween the -001 version and this -002 version of the m80c186eb data sheet. 1. operating conditions section updated to reflect 16 mhz input clock frequency limits. 2. dc specifications section: added notes regard- ing untested values: added/changed input leak- age current and input current symbols and val- ues; added 16 mhz i cc ,i id and i pd values. 3. ac specifications section: added full 16 mhz ac characteristics; added note about untested val- ues and reduced minimum output delays (t chov and t clov ) for all speeds. 4. modified errata section to reflect b-step known errata (int1 acknowledge anomaly). intel corporation, 2200 mission college blvd., santa clara, ca 95052; tel. (408) 765-8080 intel corporation (u.k.) ltd., swindon, united kingdom; tel. (0793) 696 000 intel japan k.k., ibaraki-ken; tel. 029747-8511 printed in u.s.a./m379/1296/2k/hp dm military and special products

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